This invention relates to a method for manufacturing a semiconductor device with a Schottky junction.
Recently, integrated injection logic circuits or I.sup.2 L circuits using bipolar transistors have come to public notice as semiconductor logic circuits which ensure high integration and low power consumption. Basically, one such I.sup.2 L circuit has a composite structure with the base and collector regions of a lateral PNP transistor corresponding to the emitter and base regions of a vertical NPN transistor, respectively. In the I.sup.2 L, the lateral PNP transistor serves as a current injector for the vertical NPN transistor, while the vertical NPN transistor functions as an inverter, thereby performing logical operation. Usually, however, the vertical NPN transistor is inversely constructed with respect to its collector and emitter, so that the area of the emitter-base junction is very large. Therefore, minority carriers injected through the emitter-base junction biased in the forward direction are stored in the whole base region. In consequence, the I.sup.2 L becomes susceptible to saturation, thereby inhibiting high-speed operation. Accordingly, there have conventionally been tried various methods to reduce the minority carriers stored in the base region as a whole and hence to speed up operation for the improvement of the performance of the circuit as a logic element by
(i) reducing the external base resistance, PA1 (ii) augmenting the current amplification factor, PA1 (iii) increasing the ratio of the collector area to the emitter area, and PA1 (iv) connecting a Schottky barrier diode to the collector to reduce the logic amplitude.
However, many technical problems still remain to complicate the manufacture of high speed operation I.sup.2 L circuits with satisfactory characteristics, especially I.sup.2 L circuits provided with a Schottky junction. Thus, a conventional method for manufacturing I.sup.2 L circuits with the Schottky junction involves complicated processes and low productivity, failing to provide I.sup.2 L circuits with high reliability, high integration, and low power consumption.